Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices, including floating gate flash devices and charge trap flash (CTF) devices using semiconductor-oxide-nitride-oxide-semiconductor and metal-oxide-nitride-oxide-semiconductor capacitor structures that store information in charge traps in the nitride layer, may be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Data, such as program code, user data and/or system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This data can be used in personal computer systems, among others.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged.
A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to (and in some cases, form) an access line, which is commonly referred to in the art as a “word line”. However each memory cell is not directly coupled to a data line, which is commonly referred to as a digit line (e.g., a bit line) in the art, by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source line and a data line, where the memory cells commonly coupled to a particular data line are referred to as a “column”.
Memory cells in a NAND array architecture can be programmed to a desired state. For example, electric charge can be placed on or removed from a charge storage node (e.g., a floating gate) to put the cell into one of a number of programmed states. For example, a single level cell (SLC) can represent two states (e.g., 1 or 0). Flash memory cells can also store more than two states (e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110). Such cells may be referred to as multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one digit (e.g., more than one bit). For example, a cell capable of representing four digits can have sixteen programmed states. For some MLCs, one of the sixteen programmed states can be an erased state. For these MLCs, the lowermost program state is not programmed above the erased state, that is, if the cell is programmed to the lowermost state, it remains in the erased state rather than, for example, having a charge applied to the cell during a programming operation. The other fifteen states can be referred to as “non-erased” states.
Flash memory devices can be programmed with various amounts of data at one time. The amount of data programmable at one time can be referred to as a page of data (wherein the cells storing the page of data can be referred to as a page of memory cells). In some memory devices, one page of data includes data stored on memory cells coupled to a given access line (which may be one and the same as the conductor that forms the control gate of the cell). In other memory devices, data stored in memory cells coupled to an access line can be divided into more than one page (e.g., into an “even” page and “odd” page of data). In some instances, a page of data may include data stored in memory cells coupled to more than one access line. Various amounts of data can also be erased from a flash device at the same time. The amount of data erasable at one time can be referred to as a block of data (wherein the cells corresponding to the block of data can be referred to as a block of memory cells). A block of data can include a number of data pages. A memory plane can include a number of data blocks on a given die (wherein a plane can therefore also refer to the memory cells that correspond to the data blocks). Some memory devices have multiple planes per die. For example, a die could include a plane of “even” numbered blocks and a plane of “odd” numbered blocks.
Block copy is an operation performed to move data stored in memory from one block location to another block location. For example, block copy may be done as part of memory wear leveling operations. The time to perform a block copy (e.g., Block Copy time) is usually defined by a FLASH memory specification which describes the amount of time utilized to transfer the entire data contents from one block to another block. Block Copy time may also be referred to Block Write Access Time in SD Card specifications.
Block copy time is primarily a function of the quantity of pages in the block, the page program time, and the time utilized to input and output data from the page.